In the making of a multilayer printed circuit board, a number of process steps are involved. First, a basic structure having bonded together a top layer of peel-apart-copper, a chromium layer, and a bottom copper layer having a thin zincate layer on the bottom surface thereof is laminated to an epoxy layer which contains one or more internal copper planes. The laminated structure goes through a blind via process wherein the peel-apart-copper surface is prepared for photoresist and photoresist is applied, exposed and developed to provide a pattern of dots where vias are desired. Next, the developed pattern is etched by a cupric chloride etchant, which contains 1.0 normal HCl acid, to provide blind via holes which extend down to the epoxy layer. After etching, the blind via holes are laser drilled to extend down to one or more of the internal copper planes in the epoxy or they may be made into through holes in the structure. Following the laser drilling, the via holes are cleaned and seeded and the peel-apart-copper and chromium layer is peeled and separated from the bottom copper layer which is then circuitized.
Between the etching operation and the peel-apart operation, there is a considerable lapse of time. During this time interval, it was found that due to cupric chloride residue at the bottom of the via holes which was not completely rinsed out and with time and probably humidity, free chloride ions are generated from the HCl which attack or destroy the thin zincate layer between the copper and the epoxy. The zincate will start to weaken within 12 hours and the time between the etching operation and the peel apart operation generally runs around 4 to 6 weeks. The primary function of the zincate layer is to promote adhesion between the copper and the epoxy. Thus, if the zincate layer is sufficiently weakened or destroyed by the chloride ions, peeling off of the peel-apart-copper and chromium layer will result in the bottom copper layer being torn or separated from the epoxy, particularly in the area surrounding the via holes. This creates an intolerable surface condition for circuitization of the board and results in the board being scrapped.